This invention relates to a top gate (staggered or planar) thin-film transistor and a method for producing the same. More particularly, the invention relates to a method in which a self-aligned gate is produced through the use of a laser annealing process. These thin-film transistors are suitable for use in flat panel display devices, for example active-matrix liquid-crystal displays, or in other large-area electronic devices.
Various methods have been proposed for defining self-aligned gate structures in top gate thin-film transistors. In some of these methods, the gate conductor has a width which is smaller than the spacing between the source and drain electrodes. This provides some freedom in the positioning of an insulated gate structure over the silicon body of the transistor. Various processes have been proposed for treating the silicon body of the transistor in those areas between the channel region (beneath the gate) and the source and drain electrodes. This is required to reduce the resistance of the silicon layer in regions other than the channel area of the transistor.
The use of the gate electrode in this process results in a self-aligned structure. One proposed method for reducing this resistance is by doping and laser annealing of the silicon layer on either side of the channel area of the transistor, using the insulated gate structure as a mask to protect the channel area. EP 0691688 discloses a method of manufacturing a top gate thin-film transistor using laser annealing and doping of the silicon layer to reduce the contact resistance to the source and drain electrodes.
The method disclosed in EP 0691688 will be described with reference to FIG. 1.
The transistor is formed on a glass substrate 2. An insulation film 4 overlies the glass substrate to provide a more uniform surface than that of the substrate 2. Metallic source and drain electrodes 6 and 8 are formed over the insulation film 4. These electrodes may be formed of ITO (indium tin oxide), Molybdenum or a Molybdenum alloy. The source and drain electrode 6, 8 are spaced apart, and the silicon body of the transistor fills this spacing, as will be described below.
The entire face of the substrate is treated with a plasma to diffuse dopant atoms 10 into the surface. These dopant atoms are employed to reduce the resistance of the silicon body of the transistor in regions other than the channel area of the transistor.
An amorphous silicon semiconductor layer 12 covers the spacing between the source and drain electrode 6, 8 and also partially overlies those electrodes as shown in FIG. 1. Subsequently, a gate insulation film 14 and a gate conductor layer 16 are provided, and the gate conductor layer 16 is patterned to define the gate electrode as shown in FIG. 1.
Subsequent laser irradiation 18 causes the dopant atoms 10 to diffuse into the semiconductor layer 12. The gate electrode 16 acts as a shield so that this diffusion process is inhibited in the channel area of the transistor. The laser treatment also causes the amorphous silicon 12 to melt, and during subsequent cooling the silicon becomes crystallized to form doped polysilicon source and drain regions 12a, 12b, thereby reducing the resistance between the source and drain electrodes 6, 8 and the channel area 12c of the transistor. It is desirable that there is no high-resistance undoped semiconductor material to which no gate voltage is applied, since this increases the ON-resistance of the transistor. The laser annealing and doping as described in EP 0691688 therefore reduces the ON-resistance, to improve the response characteristics of the transistor. Furthermore, the use of a gate conductor 16 having a width less than the spacing between the source and drain electrode 6, 8 assists in reducing the parasitic capacitances within the transistor structure.
A problem with the method described above is that the laser annealing of the semiconductor layer 12, to form polysilicon source and drain regions 12a, 12b, may be difficult to control for reliable results. In particular, the laser annealing process conditions are selected with a specific expected reflectance during the laser annealing process taken into consideration. This is required because the laser annealing must be controlled such that there is crystallization throughout the full depth of the semiconductor layer, but without over exposure of the structure. Slight variations in the thickness of the gate insulation film 14 dramatically affect the overall reflectance of the structure during the laser annealing process, as a result of the interference of reflected signals from different boundaries.
An alternative approach is to crystallise the amorphous silicon layer immediately after deposition. In this case, the layer is already crystallised before the laser treatment process, and this laser process is purely for activation of the dopant atoms. There is still a desire to optimise the laser treatment process, in particular to reduce the exposure of the gate to the laser energy, which can result in damage to the gate structure.
U.S. Pat. No. 5,773,844 discloses a method of manufacturing a transistor in which laser annealing is used to convert regions of the amorphous silicon body of the transistor into polycrystalline silicon regions. The gate insulator beneath the gate conductor comprises a three-layer structure. Two of the three layers extend across the full width between the source and drain electrodes of the transistor, and laser annealing is carried out through these two layers. A third gate insulator layer is patterned beneath the gate conductor prior to laser annealing, and this third patterned gate insulator layer is substantially thicker than the first two layers, and provides the operating characteristics of the insulated gate transistor.
The two gate insulator layers of U.S. Pat. No. 5,773,844 through which laser annealing is performed are very thin to provide a very low reflectance, and they act as reflectivity reducing films for reducing the reflectivity of the underlying amorphous silicon layer with respect to the laser beam.
This process requires patterning of the thicker gate insulator layer which defines the operating characteristics of the transistor, and therefore introduces an additional etching step, which could otherwise be avoided.
According to a first aspect of the invention, there is provided a method of producing a top gate thin-film transistor, comprising the steps of: forming an amorphous silicon layer over an insulating substrate; forming an insulated gate structure over the amorphous silicon layer comprising gate insulator layers and an upper gate conductor directly over the gate insulator layers, the gate conductor being patterned to be narrower than a spacing to be provided between source and drain electrode contacts to the silicon layer; laser annealing areas of the amorphous silicon layer not shielded by the gate conductor, through all of the gate insulator layers, to form polycrystalline silicon (polysilicon) portions, wherein the gate insulator layers are formed as a gate insulator layer of first refractive index, and an overlying surface insulator layer of second, lower, refractive index.
In the method of the invention, laser annealing is performed through all of the gate insulator layers, so that no additional etching steps are required.
The overlying surface insulator layer has been found to reduce fluctuations in the reflectance of the structure in dependence upon the specific thicknesses of the gate insulator layers. Therefore, the tolerances for the thicknesses of the gate insulator layers can be reduced whilst maintaining control of the laser annealing process.
The method may be applied to a staggered top gate transistor, in which case a source and drain electrode pattern is provided on the substrate before the formation of the amorphous silicon layer. Preferably, the substrate is subjected to plasma treatment to form a doped surface layer having impurity atoms diffused therein, with the laser annealing forming polysilicon portions having the impurities doped therein.
Alternatively, the method may be applied to a planar top gate transistor, in which case a source and drain electrode pattern is formed over the gate insulator, the source and drain electrodes contacting the silicon layer through wells defined in the gate insulator.
In either case, the gate insulator may comprise first and second gate insulator layers, with the first layer being patterned with the amorphous silicon layer to define the transistor body. The or each gate insulator layer may comprise silicon nitride, and the surface insulator preferably comprises silicon oxide.
According to a second aspect of the invention, there is provided a method of producing a top gate thin-film transistor, comprising the steps of:
forming an amorphous silicon layer over an insulating substrate;
treating the silicon layer to form a polysilicon layer;
forming an insulated gate structure over the amorphous silicon layer comprising gate insulator layers and an upper gate conductor directly over the gate insulator layers, the gate conductor being patterned to be narrower than a spacing to be provided between source and drain electrode contacts to the silicon layer;
implanting a dopant into the regions of the polysilicon layer not shielded by the gate conductor;
laser treating the regions of the polysilicon layer not shielded by the gate conductor to activate the dopant atoms,
wherein the gate insulator layers are formed as a gate insulator layer of first refractive index, and an overlying insulator layer of second, lower, refractive index.
In this method, the laser treatment is for activating the dopant atoms, and the silicon layer is already crystallised. The double layer gate insulator enables the reflectivity to be reduced so that the laser treatment process does not damage the transistor components. The thickness of the layers can be optimised for minimum reflectivity and also for minimum sensitivity of the reflectivity to thickness variations, as discussed above. In particular, the laser treatment process comprises exposing the structure to laser light of predetermined wavelength, the thickness of the gate insulator layers being selected depending on the wavelength, to reduce the effect of thickness variations in the gate insulator layers on the reflectance of the structure at the predetermined wavelength.
Preferably the gate insulator layers are formed as a lower gate insulator layer, the gate insulator layer of first refractive index overlying the lower gate insulator and the overlying insulator layer of second, lower, refractive index. This three layer gate insulator provides additional degrees of freedom to enable the optimisation of the reflective properties of the gate insulator.
The lower gate insulator may comprise silicon oxide, the gate insulator layer of first refractive index may comprise silicon nitride and the gate insulator of second, lower, refractive index may comprise silicon oxide. Each silicon oxide layer preferably then has a thickness of 8 to 15 nm and the silicon nitride layer has a thickness of between 15 and 30 nm.
The invention also provides a top gate thin-film transistor comprising:
a silicon layer provided over an insulating substrate;
an insulated gate structure over the silicon layer, comprising a gate insulator and an upper gate conductor, the gate conductor being patterned to be narrower than a spacing between source and drain electrode contacts to the silicon layer, the silicon layer in the region of the source and drain electrodes comprising polycrystalline silicon,
wherein the gate insulator comprises a gate insulator layer of first refractive index, and an overlying upper gate insulator layer of second, lower, refractive index, the gate conductor being provided over the upper gate insulator layer, the gate insulator layer and the upper gate insulator layer extending fully across the spacing between contacts of the source and drain to the silicon layer.
The silicon layer beneath the gate conductor may comprises amorphous silicon or polycrystalline silicon.